Signal Reception Using Non-Linearity-Compensated, Partial Response Feedback

ABSTRACT

A receiver may receive a signal that was generated by passage of symbols through a non-linear circuit. An equalizer of the receiver may equalize the received signal based on a first non-linearity compensated, inter-symbol correlated (ISC) feedback signal to generate an equalized signal. The receiver may correct a phase error of the equalized signal to generate a phase-corrected equalized signal. The phase correction may be based on a second, non-linearity compensated, inter-symbol correlated (ISC) feedback signal.

CLAIM OF PRIORITY

This patent application is a continuation of U.S. patent applicationSer. No. 14/052,859 filed on Oct. 14, 2013, which is a continuation ofU.S. patent application Ser. No. 13/755,014 filed on Jan. 31, 2013 (nowpatented as U.S. Pat. No. 8,559,496), which in turn, claims priority toU.S. Provisional Patent Application Ser. No. 61/662,085 entitled“Apparatus and Method for Efficient Utilization of Bandwidth” and filedon Jun. 20, 2012. U.S. patent application Ser. No. 14/052,859 is also anon-provisional of U.S. Provisional Patent Application Ser. No.61/726,099 entitled “Modulation Scheme Based on Partial Response” andfiled on Nov. 14, 2012, U.S. Provisional Patent Application Ser. No.61/729,774 entitled “Modulation Scheme Based on Partial Response” andfiled on Nov. 26, 2012; and U.S. Provisional Patent Application Ser. No.61/747,132 entitled “Modulation Scheme Based on Partial Response” andfiled on Dec. 28, 2012.

Each of the above-identified documents is hereby incorporated herein byreference in its entirety.

INCORPORATION BY REFERENCE

This patent application also makes reference to:

-   U.S. Pat. No. 8,582,637, titled “Low-Complexity,    Highly-Spectrally-Efficient Communications,” and filed on Jan. 31,    2013;-   U.S. Pat. No. 8,897,387, titled “Design and Optimization of Partial    Response Pulse Shape Filter,” and filed on Jan. 31, 2013;-   U.S. Pat. No. 8,675,769, titled “Constellation Map Optimization For    Highly Spectrally Efficient Communications,” and filed on Jan. 31,    2013;-   U.S. Pat. No. 8,571,131, titled “Dynamic Filter Adjustment for    Highly-Spectrally-Efficient Communications,” and filed on Jan. 31,    2013;-   U.S. Pat. No. 8,559,494, titled “Timing Synchronization for    Reception of Highly-Spectrally-Efficient Communications,” and filed    on Jan. 31, 2013;-   U.S. Pat. No. 8,599,914, titled “Feed Forward Equalization for    Highly-Spectrally-Efficient Communications,” and filed on Jan. 31,    2013;-   U.S. Pat. No. 8,665,941, titled “Decision Feedback Equalizer for    Highly-Spectrally-Efficient Communications,” and filed on Jan. 31,    2013;-   U.S. Pat. No. 8,873,612, titled “Decision Feedback Equalizer with    Multiple Cores for Highly-Spectrally-Efficient Communications,” and    filed on Jan. 31, 2013;-   U.S. Pat. No. 8,559,498, titled “Decision Feedback Equalizer    Utilizing Symbol Error Rate Biased Adaptation Function for    Highly-Spectrally-Efficient Communications,” and filed on Jan. 31,    2013;-   U.S. Pat. No. 8,548,097, titled “Coarse Phase Estimation for    Highly-Spectrally-Efficient Communications,” and filed on Jan. 31,    2013;-   U.S. Pat. No. 8,565,363, titled “Fine Phase Estimation for Highly    Spectrally Efficient Communications,” and filed on Jan. 31, 2013;    and-   U.S. Pat. No. 8,605,832, titled “Joint Sequence Estimation of Symbol    and Phase with High Tolerance of Nonlinearity,” and filed on Jan.    31, 2013.

Each of the above stated applications is hereby incorporated herein byreference in its entirety.

TECHNICAL FIELD

Aspects of the present application relate to electronic communications.

BACKGROUND

Existing communications methods and systems are overly power hungryand/or spectrally inefficient. Further limitations and disadvantages ofconventional and traditional approaches will become apparent to one ofskill in the art, through comparison of such approaches with someaspects of the present method and system set forth in the remainder ofthis disclosure with reference to the drawings.

BRIEF SUMMARY

Methods and systems are provided for signal reception usingnon-linearity-compensated, partial response feedback, substantially asillustrated by and/or described in connection with at least one of thefigures, as set forth more completely in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram depicting an example system configured forlow-complexity, highly-spectrally-efficient communications.

FIG. 2 is a block diagram depicting an example equalization and sequenceestimation circuit for use in a system configured for low-complexity,highly-spectrally-efficient communications.

FIG. 3 is a block diagram depicting an example sequence estimationcircuit for use in a system configured for low-complexity,highly-spectrally-efficient communications.

FIG. 4 is a block diagram depicting an example metric calculationcircuit for use in a system configured for low-complexity,highly-spectrally-efficient communications.

FIGS. 5A-5D depict portions of an example sequence estimation processperformed by a system configured for low-complexity,highly-spectrally-efficient communications.

FIGS. 6A and 6B depict an example survivor selection process that is analternative to the process depicted in FIG. 5D.

FIG. 7 is a diagram illustrating initialization of the sequenceestimation process.

FIG. 8A depicts an example implementation of the phase buffer shown inFIG. 3.

FIG. 8B depicts an example implementation of the symbol buffer shown inFIG. 3.

FIG. 8C depicts contents of an example symbol buffer over a plurality ofiterations of a sequence estimation process.

FIG. 8D depicts generated signals corresponding to the symbol buffercontents shown in FIG. 8C.

FIG. 9A is a flowchart illustrating an example process for carrierrecovery and phase error correction using a partial response feedbacksignal.

FIG. 9B is a flowchart illustrating an example process for equalizationof a partial response signal using a partial response feedback signal.

FIG. 10 is a flowchart illustrating adaptation of feedback loopbandwidth.

DETAILED DESCRIPTION

As utilized herein the terms “circuits” and “circuitry” refer tophysical electronic components (i.e. hardware) and any software and/orfirmware (“code”) which may configure the hardware, be executed by thehardware, and or otherwise be associated with the hardware. As usedherein, for example, a particular processor and memory may comprise afirst “circuit” when executing a first one or more lines of code and maycomprise a second “circuit” when executing a second one or more lines ofcode. As utilized herein, “and/or” means any one or more of the items inthe list joined by “and/or”. As an example, “x and/or y” means anyelement of the three-element set {(x), (y), (x, y)}. As another example,“x, y, and/or z” means any element of the seven-element set {(x), (y),(z), (x, y), (x, z), (y, z), (x, y, z)}. As utilized herein, the term“exemplary” means serving as a non-limiting example, instance, orillustration. As utilized herein, the terms “e.g.,” and “for example”set off lists of one or more non-limiting examples, instances, orillustrations. As utilized herein, circuitry is “operable” to perform afunction whenever the circuitry comprises the necessary hardware andcode (if any is necessary) to perform the function, regardless ofwhether performance of the function is disabled, or not enabled, by someuser-configurable setting.

FIG. 1 is a block diagram depicting an example system configured forlow-complexity, highly-spectrally-efficient communications. The system100 comprises a mapper circuit 102, a pulse shaping filter circuit 104,a timing pilot insertion circuit 105, a transmitter front-end circuit106, a channel 107, a receiver front-end 108, a filter circuit 109, atiming pilot removal circuit 110, an equalization and sequenceestimation circuit 112, and a de-mapping circuit 114. The components102, 104, 105, and 106 may be part of a transmitter (e.g., a basestation or access point, a router, a gateway, a mobile device, a server,a computer, a computer peripheral device, a table, a modem, a set-topbox, etc.), the components 108, 109, 110, 112, and 114 may be part of areceiver (e.g., a base station or access point, a router, a gateway, amobile device, a server, a computer, a computer peripheral device, atable, a modem, a set-top box, etc.), and the transmitter and receivermay communicate via the channel 107.

The mapper 102 may be operable to map bits of the Tx_bitstream to betransmitted to symbols according to a selected modulation scheme. Thesymbols may be output via signal 103. For example, for an quadratureamplitude modulation scheme having a symbol alphabet of N (N-QAM), themapper may map each Log₂(N) bits of the Tx_bitstream to single symbolrepresented as a complex number and/or as in-phase (I) andquadrature-phase (Q) components. Although N-QAM is used for illustrationin this disclosure, aspects of this disclosure are applicable to anymodulation scheme (e.g., amplitude shift keying (ASK), phase shiftkeying (PSK), frequency shift keying (FSK), etc.). Additionally, pointsof the N-QAM constellation may be regularly spaced (“on-grid”) orirregularly spaced (“off-grid”). Furthermore, the symbol constellationused by the mapper may be optimized for best bit-error rate performancethat is related to log-likelihood ratio (LLR) and to optimizing meanmutual information bit (MMIB). The Tx_bitstream may, for example, be theresult of bits of data passing through a forward error correction (FEC)encoder and/or an interleaver. Additionally, or alternatively, thesymbols out of the mapper 102 may pass through an interleaver.

The pulse shaper 104 may be operable to adjust the waveform of thesignal 103 such that the waveform of the resulting signal 113 complieswith the spectral requirements of the channel over which the signal 113is to be transmitted. The spectral requirements may be referred to asthe “spectral mask” and may be established by a regulatory body (e.g.,the Federal Communications Commission in the United States or theEuropean Telecommunications Standards Institute) and/or a standards body(e.g., Third Generation Partnership Project) that governs thecommunication channel(s) and/or standard(s) in use. The pulse shaper 104may comprise, for example, an infinite impulse response (IIR) and/or afinite impulse response (FIR) filter. The number of taps, or “length,”of the pulse shaper 104 is denoted herein as LTx, which is an integer.The impulse response of the pulse shaper 104 is denoted herein as hTx.The pulse shaper 104 may be configured such that its output signal 113intentionally has a substantial amount of inter-symbol interference(ISI). Accordingly, the pulse shaper 104 may be referred to as a partialresponse pulse shaping filter, and the signal 113 may be referred to asa partial response signal or as residing in the partial response domain,whereas the signal 103 may be referred to as residing in the symboldomain. The number of taps and/or the values of the tap coefficients ofthe pulse shaper 104 may be designed such that the pulse shaper 104 isintentionally non-optimal for additive white Gaussian noise (AWGN) inorder to improve tolerance of non-linearity in the signal path. In thisregard, the pulse shaper 104 may offer superior performance in thepresence of non-linearity as compared to, for example, a conventionalnear zero positive ISI pulse shaping filter (e.g., root raised cosine(RRC) pulse shaping filter). The pulse shaper 104 may be designed asdescribed in one or more of: the United States patent application titled“Design and Optimization of Partial Response Pulse Shape Filter,” theUnited States patent application titled “Constellation Map OptimizationFor Highly Spectrally Efficient Communications,” and the United Statespatent application titled “Dynamic Filter Adjustment ForHighly-Spectrally-Efficient Communications,” each of which isincorporated herein by reference, as set forth above.

It should be noted that a partial response signal (or signals in the“partial response domain”) is just one example of a type of signal forwhich there is correlation among symbols of the signal (referred toherein as “inter-symbol-correlated (ISC) signals”). Such ISC signals arein contrast to zero (or near-zero) ISI signals generated by, forexample, raised-cosine (RC) or root-raised-cosine (RRC) filtering. Forsimplicity of illustration, this disclosure focuses on partial responsesignals generated via partial response filtering. Nevertheless, aspectsof this disclosure are applicable to other ISC signals such as, forexample, signals generated via matrix multiplication (e.g., latticecoding), and signals generated via decimation below the Nyquistfrequency such that aliasing creates correlation between symbols.

The timing pilot insertion circuit 105 may insert a pilot signal whichmay be utilized by the receiver for timing synchronization. The outputsignal 115 of the timing pilot insertion circuit 105 may thus comprisethe signal 113 plus an inserted pilot signal (e.g., a sine wave at¼×fbaud, where (baud is the symbol rate). An example implementation ofthe pilot insertion circuit 105 is described in the United States patentapplication titled “Timing Synchronization for Reception ofHighly-Spectrally-Efficient Communications,” which is incorporatedherein by reference, as set forth above.

The transmitter front-end 106 may be operable to amplify and/orupconvert the signal 115 to generate the signal 116. Thus, thetransmitter front-end 106 may comprise, for example, a power amplifierand/or a mixer. The front-end may introduce non-linear distortion and/orphase noise (and/or other non-idealities) to the signal 116. Thenon-linearity of the circuit 106 may be represented as FnlTx which maybe, for example, a polynomial, or an exponential (e.g., Rapp model). Thenon-linearity may incorporate memory (e.g., Voltera series).

The channel 107 may comprise a wired, wireless, and/or opticalcommunication medium. The signal 116 may propagate through the channel107 and arrive at the receive front-end 108 as signal 118. Signal 118may be noisier than signal 116 (e.g., as a result of thermal noise inthe channel) and may have higher or different ISI than signal 116 (e.g.,as a result of multi-path).

The receiver front-end 108 may be operable to amplify and/or downconvertthe signal 118 to generate the signal 119. Thus, the receiver front-endmay comprise, for example, a low-noise amplifier and/or a mixer. Thereceiver front-end may introduce non-linear distortion and/or phasenoise to the signal 119. The non-linearity of the circuit 108 may berepresented as FnlRx which may be, for example, a polynomial, or anexponential (e.g., Rapp model). The non-linearity may incorporate memory(e.g., Voltera series).

The timing pilot recovery and removal circuit 110 may be operable tolock to the timing pilot signal inserted by the pilot insertion circuit105 in order to recover the symbol timing of the received signal. Theoutput 122 may thus comprise the signal 120 minus (i.e., without) thetiming pilot signal. An example implementation of the timing pilotrecovery and removal circuit 110 is described in the United Statespatent application titled “Timing Synchronization for Reception ofHighly-Spectrally-Efficient Communications,” which is incorporatedherein by reference, as set forth above.

The input filter 109 may be operable to adjust the waveform of thepartial response signal 119 to generate partial response signal 120. Theinput filter 109 may comprise, for example, an infinite impulse response(IIR) and/or a finite impulse response (FIR) filter. The number of taps,or “length,” of the input filter 109 is denoted herein as LRx, aninteger. The impulse response of the input filter 109 is denoted hereinas hRx. The number of taps, and/or tap coefficients of the pulse shaper109 may be configured based on: a non-linearity model,

, signal-to-noise ratio (SNR) of signal 120, the number of taps and/ortap coefficients of the Tx partial response filter 104, and/or otherparameters. The number of taps and/or the values of the tap coefficientsof the input filter 109 may be configured such that noise rejection isintentionally compromised (relative to a perfect match filter) in orderto improve performance in the presence of non-linearity. As a result,the input filter 109 may offer superior performance in the presence ofnon-linearity as compared to, for example, a conventional near zeropositive ISI matching filter (e.g., root raised cosine (RRC) matchedfilter). The input filter 109 may be designed as described in one ormore of: the United States patent application titled “Design andOptimization of Partial Response Pulse Shape Filter,” the United Statespatent application titled “Constellation Map Optimization For HighlySpectrally Efficient Communications,” and the United States patentapplication titled “Dynamic Filter Adjustment ForHighly-Spectrally-Efficient Communications,” each of which isincorporated herein by reference, as set forth above.

As utilized herein, the “total partial response (h)” may be equal to theconvolution of hTx and hRx, and, thus, the “total partial responselength (L)”may be equal to LTx+LRx−1. L may, however, be chosen to beless than LTx+LRx−1 where, for example, one or more taps of the Tx pulseshaper 104 and/or the Rx input filter 109 are below a determined level.Reducing L may reduce decoding complexity of the sequence estimation.This tradeoff may be optimized during the design of the system 100.

The equalizer and sequence estimator 112 may be operable to perform anequalization process and a sequence estimation process. The equalizermay utilize a least mean square (LMS) algorithm that attempts minimizethe least mean square of an error between the partial response feedbacksignal 203 and the equalizer output 222. Details of an exampleimplementation of the equalizer and sequence estimator 112 are describedbelow with respect to FIG. 2. The output signal 132 of the equalizer andsequence estimator 112 may be in the symbol domain and may carryestimated values of corresponding transmitted symbols (and/or estimatedvalues of the corresponding transmitted information bits of theTx_bitstream) of signal 103. Although not depicted, the signal 132 maypass through an interleaver en route to the de-mapper 114. The estimatedvalues may comprise soft-decision estimates, hard-decision estimates, orboth.

The de-mapper 114 may be operable to map symbols to bit sequencesaccording to a selected modulation scheme. For example, for an N-QAMmodulation scheme, the mapper may map each symbol to Log₂(N) bits of theRx_bitstream. The Rx_bitstream may, for example, be output to ade-interleaver and/or an FEC decoder. Alternatively, or additionally,the de-mapper 114 may generate a soft output for each bit, referred asLLR (Log-Likelihood Ratio). The soft output bits may be used by asoft-decoding forward error corrector (e.g. a low-density parity check(LDPC) dedecoder). The soft output bits may be generated using, forexample, a Soft Output Viterbi Algorithm (SOVA) or similar. Suchalgorithms may use additional information of the sequence decodingprocess including metrics levels of dropped paths and/or estimated bitprobabilities for generating the LLR, where

${{{LLR}(b)} = {\log \left( \frac{P_{b}}{1 - P_{b}} \right)}},$

where P_(b) is the probability that bit b=1.

In an example implementation, components of the system upstream of thepulse shaper 104 in the transmitter and downstream of the equalizer andsequence estimator 112 in the receiver may be as found in a conventionalN-QAM system. Thus, through modification of the transmit side physicallayer and the receive side physical layer, aspects of the invention maybe implemented in an otherwise conventional N-QAM system in order toimprove performance of the system in the presence of non-linearity ascompared, for example, to use of RRC filters and an N-QAM slicer.

FIG. 2 is a block diagram depicting an example equalization and sequenceestimation circuit for use in a system configured for low-complexity,highly-spectrally-efficient communications. Shown are an equalizercircuit 202, a signal combiner circuit 204, a phase adjust circuit 206,a sequence estimation circuit 210, and non-linearity modeling circuits236 a and 236 b.

The equalizer 202 may be operable to process the signal 122 to reduceISI caused by the channel 107. The output 222 of the equalizer 202 is apartial response domain signal. The ISI of the signal 222 is primarilythe result of the pulse shaper 104 and the input filter 109 (there maybe some residual ISI from multipath, for example, due to use of theleast means square (LMS) approach in the equalizer 202). The errorsignal, 201, fed back to the equalizer 202 is also in the partialresponse domain. The signal 201 is the difference, calculated bycombiner 204, between 222 and a partial response signal 203 that isoutput by non-linearity modeling circuit 236 a. An exampleimplementation of the equalizer is described in the United States patentapplication titled “Feed Forward Equalization forHighly-Spectrally-Efficient Communications,” which is incorporatedherein by reference, as set forth above.

The carrier recovery circuit 208 may be operable to generate a signal228 based on a phase difference between the signal 222 and a partialresponse signal 207 output by the non-linearity modeling circuit 236 b.The carrier recovery circuit 208 may be as described in the UnitedStates patent application titled “Coarse Phase Estimation forHighly-Spectrally-Efficient Communications,” which is incorporatedherein by reference, as set forth above.

The phase adjust circuit 206 may be operable to adjust the phase of thesignal 222 to generate the signal 226. The amount and direction of thephase adjustment may be determined by the signal 228 output by thecarrier recovery circuit 208. The signal 226 is a partial responsesignal that approximates (up to an equalization error caused by finitelength of the equalizer 202, a residual phase error not corrected by thephase adjust circuit 206, non-linearities, and/or other non-idealities)the total partial response signal resulting from corresponding symbolsof signal 103 passing through pulse shaper 104 and input filter 109.

The buffer 212 buffers samples of the signal 226 and outputs a pluralityof samples of the signal 226 via signal 232. The signal 232 is denotedPR1, where the underlining indicates that it is a vector (in this caseeach element of the vector corresponds to a sample of a partial responsesignal). In an example implementation, the length of the vector PR1 maybe Q samples.

Input to the sequence estimation circuit 210 are the signal 232, thesignal 228, and a response ĥ. Response ĥ is based on h (the totalpartial response, discussed above). For example, response ĥ mayrepresent a compromise between h (described above) and a filter responsethat compensates for channel non-idealities such as multi-path. Theresponse ĥ may be conveyed and/or stored in the form of LTx+LRx−1 tapcoefficients resulting from convolution of the LTx tap coefficients ofthe pulse shaper 104 and the LRx tap coefficients of the input filter109. Alternatively, response ĥ may be conveyed and/or stored in the formof fewer than LTx+LRx−1 tap coefficients—for example, where one or moretaps of the LTx and LRx is ignored due to being below a determinedthreshold. The sequence estimation circuit 210 may output partialresponse feedback signals 205 and 209, a signal 234 that corresponds tothe finely determined phase error of the signal 120, and signal 132(which carries hard and/or soft estimates of transmitted symbols and/ortransmitted bits). An example implementation of the sequence estimationcircuit 210 is described below with reference to FIG. 3.

The non-linear modeling circuit 236 a may apply a non-linearity function

(a model of the non-linearity seen by the received signal en route tothe circuit 210) to the signal 205 resulting in the signal 203.Similarly, the non-linear modeling circuit 236 b may apply thenon-linearity function

to the signal 209 resulting in the signal 207.

may be, for example, a third-order or fifth-order polynomial. Increasedaccuracy resulting from the use of a higher-order polynomial for

may tradeoff with increased complexity of implementing a higher-orderpolynomial. Where FnlTx is the dominant non-linearity of thecommunication system 100,

modeling only FnlTx may be sufficient. Where degradation in receiverperformance is above a threshold due to other non-linearities in thesystem (e.g., non-linearity of the receiver front-end 108) the model

may take into account such other non-linearities

FIG. 3 is a block diagram depicting an example sequence estimationcircuit for use in a system configured for low-complexity,highly-spectrally-efficient communications. Shown are a candidategeneration circuit 302, a metrics calculation circuit 304, a candidateselection circuit 306, a combiner circuit 308, a buffer circuit 310, abuffer circuit 312, a phase adjust circuit 314, and convolution circuits316 a and 316 b. The sequence estimation process described with respectto FIG. 3 is an example only. Many variations of the sequence estimationprocess are also possible. For example, although the implementationdescribed here uses one phase survivor per symbol survivor, anotherimplementation may have PSu (e.g., PSu<Su) phase survivors that will beused commonly for each symbol survivor.

For each symbol candidate at time n, the metrics calculation circuit 304may be operable to generate a metric vector D_(n) ¹ . . . D_(n)^(M×Su×P) based on the partial response signal PR1, the signal 303 aconveying the phase candidate vectors PC_(n) ¹ . . . PC_(n) ^(M×Su×P),and the signal 303 b conveying the symbol candidate vectors SC_(n) ¹ . .. SC_(n) ^(M×Su×P), where underlining indicates a vector, subscript nindicates that it is the candidate vectors for time n, M is an integerequal to the size of the symbol alphabet (e.g., for N-QAM, M is equal toN), Su is an integer equal to the number of symbol survivor vectorsretained for each iteration of the sequence estimation process, and P isan integer equal to the size of the phase alphabet. In an exampleimplementation, the size of phase alphabet is three, with each of thethree symbols corresponding to one of: a positive shift, a negativephase shift, or zero phase shift, as further described below withrespect to FIGS. 5A-5D and in the United States patent applicationtitled “Fine Phase Estimation for Highly Spectrally EfficientCommunications,” which is incorporated herein by reference, as set forthabove. In an example implementation, each phase candidate vector maycomprise Q phase values and each symbol candidate vector may comprise Qsymbols. An example implementation of the metrics calculation block isdescribed below with reference to FIG. 4.

The candidate selection circuit 306 may be operable to select Su of thesymbol candidates SC_(n) ¹ . . . SC_(n) ^(M×Su×P) and Su of the phasecandidates PC_(n) ¹ . . . PC_(n) ^(M×Su×P) based on the metrics D_(n) ¹. . . D_(n) ^(M×Su×P). The selected phase candidates are referred to asthe phase survivors PS_(n) ¹ . . . PS_(n) ^(Su). Each element of eachphase survivors PS_(n) ¹ . . . PS_(n) ^(Su) may correspond to anestimate of residual phase error in the signal 232. That is, the phaseerror remaining in the signal after coarse phase error correction viathe phase adjust circuit 206. The best phase survivor PS_(n) ¹ isconveyed via signal 307 a. The Su phase survivors are retained for thenext iteration of the sequence estimation process (at which time theyare conveyed via signal 301 b). The selected symbol candidates arereferred to as the symbol survivors SS_(n) ¹ . . . SS_(n) ^(Su). Eachelement of each symbol survivors SS_(n) ¹ . . . SS_(n) ^(Su) maycomprise a soft-decision estimate and/or a hard-decision estimate of asymbol of the signal 232. The best symbol survivor SS_(n) ¹ is conveyedto symbol buffer 310 via the signal 307 b. The Su symbol survivors areretained for the next iteration of the sequence estimation process (atwhich time they are conveyed via signal 301 a). Although, the exampleimplementation described selects the same number, Su, of phase survivorsand symbol survivors, such is not necessarily the case. Operation ofexample candidate selection circuits 306 are described below withreference to FIGS. 5D and 6A-6B.

The candidate generation circuit 302 may be operable to generate phasecandidates PC_(n) ¹ . . . PC_(n) ^(M×Su×P) and symbol candidates SC_(n)¹ . . . SC_(n) ^(M×Su×P) from phase survivors PS_(n−1) ¹ . . . PS_(n−1)^(Su) and symbol survivors SS_(n−1) ¹ . . . SS_(n−1) ^(Su), wherein theindex n−1 indicates that they are survivors from time n−1 are used forgenerating the candidates for time n. In an example implementation,generation of the phase and/or symbol candidates may be as, for example,described below with reference to FIGS. 5A and 5B and/or in the UnitedStates patent application titled “Joint Sequence Estimation of Symboland Phase with High Tolerance of Nonlinearity,” which is incorporatedherein by reference, as set forth above.

The symbol buffer circuit 310 may comprise a plurality of memoryelements operable to store one or more symbol survivor elements of oneor more symbol survivor vectors. The phase buffer circuit 312 maycomprise a plurality of memory elements operable to store one or morephase survivor vectors. Example implementations of the buffers 310 and312 are described below with reference to FIGS. 8A and 8B, respectively.

The combiner circuit 308 may be operable to combine the best phasesurvivor, PS_(n) ¹, conveyed via signal 307 a, with the signal 228generated by the carrier recovery circuit 208 (FIG. 2) to generate finephase error vector FPE_(n) ¹, conveyed via signal 309, which correspondsto the finely estimated phase error of the signal 222 (FIG. 2). At eachtime n, fine phase error vector FPE_(n−1) ¹ stored in phase buffer 312may be overwritten by FPE_(n) ¹.

The phase adjust circuit 314 may be operable to adjust the phase of thesignal 315 a by an amount determined by the signal 234 output by phasebuffer 312, to generate the signal 205.

The circuit 316 a, which performs a convolution, may comprise a FIRfilter or IIR filter, for example. The circuit 316 a may be operable toconvolve the signal 132 with response ĥ, resulting in the partialresponse signal 315 a. Similarly, the convolution circuit 316 b may beoperable to convolve the signal 317 with response ĥ, resulting in thepartial response signal 209. As noted above, response ĥ may be storedby, and/or conveyed to, the sequence estimation circuit 210 in the formof one or more tap coefficients, which may be determined based on thetap coefficients of the pulse shaper 104 and/or input filter 109 and/orbased on an adaptation algorithm of a decision feedback equalizer (DFE).Response ĥ may thus represent a compromise between attempting toperfectly reconstruct the total partial response signal (103 as modifiedby pulse shaper 104 and input filter 109) on the one hand, andcompensating for multipath and/or other non-idealities of the channel107 on the other hand. In this regard, the system 100 may comprise oneor more DFEs as described in one or more of: the United States patentapplication titled “Decision Feedback Equalizer forHighly-Spectrally-Efficient Communications,” the United States patentapplication titled “Decision Feedback Equalizer with Multiple Cores forHighly-Spectrally-Efficient Communications,” and the United Statespatent application titled “Decision Feedback Equalizer Utilizing SymbolError Rate Biased Adaptation Function for Highly-Spectrally-EfficientCommunications,” each of which is incorporated herein by reference, asset forth above.

Thus, signal 203 is generated by taking a first estimate of transmittedsymbols, (an element of symbol survivor SS_(n) ¹), converting the firstestimate of transmitted symbols to the partial response domain viacircuit 316 a, and then compensating for non-linearity in thecommunication system 100 via circuit 236 a (FIG. 2). Similarly, signal207 is generated from a second estimate of transmitted symbols (anelement of symbol survivor SS_(n) ¹) that is converted to the partialresponse domain by circuit 316 b to generate signal 209, and thenapplying a non-linear model to the signal 209 b to compensate fornon-linearity in the signal path.

FIG. 4 is a block diagram depicting an example metric calculationcircuit for use in a system configured for low-complexity,highly-spectrally-efficient communications. Shown is a phase adjustcircuit 402, a convolution circuit 404, and a cost function calculationcircuit 406. The phase adjust circuit 402 may phase shift one or moreelements of the vector PR1 (conveyed via signal 232) by a correspondingone or more values of the phase candidate vectors PC_(n) ¹ . . . PC_(n)^(M×Su×P). The signal 403 output by the phase adjust circuit 402 thusconveys a plurality of partial response vectors PR2_(n) ¹ . . . PR2_(n)^(M×Su×P), each of which comprises a plurality of phase-adjustedversions of PR1.

The circuit 404, which performs a convolution, may comprise a FIR filteror IIR filter, for example. The circuit 404 may be operable to convolvethe symbol candidate vectors SC_(n) ¹ . . . SC_(n) ^(M×Su×P) with ĥ. Thesignal 405 output by the circuit 404 thus conveys vectors SCPR_(n) ¹ . .. SCPR_(n) ^(M×Su×P), each of which is a candidate partial responsevector.

The cost function circuit 406 may be operable to generate metricsindicating the similarity between one or more of the partial responsevectors PR2_(n) ¹ . . . PR2_(n) ^(M×Su×P) and one or more of the vectorsSCPR_(n) ¹ . . . SCPR_(n) ^(M×Su×P) to generate error metrics D_(n) ¹ .. . D_(n) ^(M×Su×P). In an example implementation, the error metrics maybe Euclidean distances calculated as shown below in equation 1.

D _(i) ^(n)=|(SCPR _(n) ^(i))−(PR2_(n) ^(i))|²   EQ. 1

for 1≦i≦M×Su×P.

FIGS. 5A-5D depict portions of an example sequence estimation processperformed by a system configured for low-complexity,highly-spectrally-efficient communications. In FIGS. 5A-5D it isassumed, for purposes of illustration, that M=4 (a symbol alphabet ofα,β,χ,δ, Su=3 (three symbol survivors are selected each iteration),Psu=Su (three phase survivors are selected each iteration), P=3 (a phasealphabet of plus, minus, and zero), and that Q (vector length) is 4.

Referring to FIG. 5A, there is shown phase and symbol survivors fromtime n−1 on the left side of the figure. The first step in generatingsymbol candidates and phase candidates from the survivors is toduplicate the survivors and shift the contents to free up an element ineach of the resulting vectors called out as 502 on the right side ofFIG. 5A. In the example implementation depicted, the survivors areduplicated M*P−1 times and shifted one element.

Referring to FIG. 5B, the next step in generating the candidates isinserting symbols in the vacant elements of the symbol vectors and phasevalues in the vacant elements of the phase vectors, resulting in thesymbol candidates and phase candidate for time n (called out as 504 inFIG. 5B). In the example implementation depicted, each of the M possiblesymbol values is inserted into Su*P symbol candidates, and each of the Pphase values may be inserted into M*Su candidates. In the exampleimplementation depicted, θ5 is a reference phase value calculated basedon phase survivor PS_(n−1) ¹. For example, θ5 may be the average (or aweighted average) of the last two or more elements of the phase survivorPS_(n−1) ¹ (in the example shown, the average over the last two elementswould be (θ5+0)/2). In the example implementation depicted, θ4=θ5−Δθ,and θ6=θ5+Δθ, where Δθ is based on: the amount of phase noise in signal226, slope (derivative) of the phase noise in signal 226,signal-to-noise ratio (SNR) of signal 226, and/or capacity of thechannel 107. Similarly, in the example implementation shown, θ8 is areference phase value calculated based on phase survivor PS_(n−1) ²,θ7=θ8 −Δθ, θ9=θ8+Δθ, θ11 is a reference phase value calculated based onphase survivor PS_(n−1) ³, θ10=θ11−Δθ, and θ12=θ11+Δθ.

Referring to FIG. 5C, as described above with reference to FIG. 4, thesymbol candidates are transformed to the partial response domain via aconvolution, the reference signal PR1 is phase adjusted, and then themetrics D_(n) ¹ . . . D_(n) ^(M×Su×P) are calculated based on thepartial response signals PR2_(n) ¹ . . . PR2_(n) ^(M×Su×P) and SCPR_(n)¹ . . . SCPR_(n) ^(M×Su×P).

Referring to FIG. 5D, the metrics calculated in FIG. 5C are used toselect which of the candidates generated in FIG. 5B are selected to bethe survivors for the next iteration of the sequence estimation process.FIG. 5D depicts an example implementation in which the survivors areselected in a single step by simply selecting Su candidatescorresponding to the Su best metrics. In the example implementationdepicted, it is assumed that metric D_(n) ¹⁴ is the best metric, thatD_(n) ¹⁶ is the second best metric, and that D_(n) ³⁰ is the third-bestmetric. Accordingly, symbol candidate SC_(n) ¹⁴ is selected as the bestsymbol survivor, PC_(n) ¹⁴ is selected as the best phase survivor,symbol candidate SC_(n) ¹⁶ is selected as the second-best symbolsurvivor, PC_(n) ¹⁶ is selected as the second-best phase survivor,symbol candidate SC_(n) ³⁰ is selected as the third-best symbolsurvivor, and PC_(n) ³⁰ is selected as the third-best phase survivor.The survivor selection process of FIG. 5D may result in selectingidentical symbol candidates which may be undesirable. A survivorselection process that prevents redundant symbol survivors is describedbelow with reference to FIGS. 6A and 6B.

FIGS. 6A and 6B depict an example survivor selection process that is analternative to the process depicted in FIG. 5D. In FIG. 6A, thecandidates generated in FIG. 5B and the metrics calculated in FIG. 5Care used to select the best phase candidate for each symbol candidate(selected candidates are called out by reference designator 602). InFIG. 6B, the best Su of the candidates selected in FIG. 6A are selectedas the survivors for the next iteration of the sequence estimationprocess. In the example implementation depicted, it is assumed thatmetric D_(n) ⁶ is the best metric, that D_(n) ⁵ is the second-bestmetric, and that D_(n) ²⁵ is the third-best metric. Accordingly, symbolcandidate SC_(n) ⁶ is selected as the best symbol survivor, PC_(n) ⁶ isselected as the best phase survivor, symbol candidate SC_(n) ⁵ isselected as the second-best symbol survivor, PC_(n) ⁵ , is selected asthe second-best phase survivor, symbol candidate SC_(n) ²⁵ is selectedas the third-best symbol survivor, and PC_(n) ²⁵ is selected as thethird-best phase survivor.

Although the implementations described with reference to FIGS. 5A-6B useone phase survivor per symbol survivor. Other example implementationsmay use PSu (e.g., PSu<Su) phase survivors that are used commonly foreach symbol survivor. In such an implementation, each of the phasesurvivors PS_(n−1) ^(n) . . . PS_(n−1) ^(PSu) may be duplicated P timesto generate phase successors, and then duplicated M*Su times to beassociated with corresponding symbols successors. The number of symbolcandidates in such an implementation would be M*Su*PSu*P.

FIG. 7 is a diagram illustrating initialization of the sequenceestimation process. In FIG. 7 it is again assumed, for illustration,that M=4 (a symbol alphabet of α,β,χ,δ), Su=3 (three symbol survivorsare selected each iteration), Psu=Su (three phase survivors are selectedeach iteration), P=3 (a phase alphabet of plus, minus, and zero), andthat Q (vector length) is 4. On the far left of FIG. 7 is shown symbolsurvivors 702 after receipt of a preamble sequence. Because the preambleis a deterministic sequence, all symbol survivors are forced to the samevalues. From the survivors 702 are generated the candidates 704 andmetrics 706 are calculated based on the candidates 704. In the exampleimplementation shown, since the survivors were all the same, there areonly four unique symbol candidates. The metrics for the four candidatesare, respectively, D1, D2, D3, and D4. Accordingly, if the threecandidates corresponding to the best three metrics were chosen, then thethree candidates corresponding to D1 would all be chosen and thesurvivors for the next iteration would again all be identical.Accordingly, the three best, non-redundant symbol candidates areselected (as indicated by the heavy lines). Consequently, one of thecandidates having the metric value D1 is selected, one of the candidateshaving the metric value D2 is selected, and one of the candidates havingmetric value D3 is selected, such that three non-redundant survivors areused for the next iteration.

FIG. 8A depicts an example implementation of the phase buffer shown inFIG. 3. In the example implementation depicted, the depth of the phasebuffer 312 is Q and the phase value stored at element q is representedas Z_(q), for q from 1 to Q. In the example implementation depicted, thevalue stored in element q3 is output as the signal 234. For eachiteration of the sequence estimation process, Q elements of the phasebuffer 312 storing Q values of PS_(n−1) ¹ may be overwritten with Qvalues of PS_(n) ¹.

FIG. 8B depicts an example implementation of the symbol buffer shown inFIG. 3. In the example implementation depicted, the depth of the symbolbuffer 310 is Q and the symbol value stored at element q is representedas X_(q), for q from 1 to Q. For each iteration of the sequenceestimation process, Q elements of the symbol buffer 310 storing Q valuesof SS_(n−1) ¹ may be overwritten with Q values of SS_(n) ¹. In theexample implementation depicted, the value(s) stored in one or moreelements starting with index q1 (e.g., values stored in elements q1through q1+L−1) is/are output as the signal 317 and the value(s) storedin one or more elements starting with index q2 (e.g., values stored inelements q2 through q2+L−1) is/are output as the signal 132. Because thevalue(s) output as the signal 317 start from a lower-indexed element ofthe symbol buffer, the delay between receiving a signal sample andoutputting the corresponding value of signal 317 is shorter than thedelay between receiving a signal sample and outputting the correspondingvalue of the signal 132. Because the value(s) output as the signal 132start from a higher-indexed element, however, it/they is/are likely tobe less error-prone. These concepts are further illustrated withreference to in FIGS. 8C and 8D. In an example implementation, q2 isequal to q3.

FIG. 8C depicts contents of an example symbol buffer over a plurality ofiterations of a sequence estimation process. In the exampleimplementation shown in FIG. 8C, the symbol buffer 310 comprises fourelements with the signal 317 corresponding to the contents of the firstelement (for simplicity of illustration, in FIGS. 8C and 8D, it isassumed only one element is output as signal 317 on each iteration) andthe signal 132 corresponding to the fourth element (for simplicity ofillustration, in FIGS. 8C and 8D, it is assumed only one element isoutput as signal 132 on each iteration). In the example implementationdepicted, during each iteration of the sequence estimation process,candidates are generated by duplicating the survivors from the previousiteration, shifting the values by one element, and the appending a newvalue into the vacated element. Accordingly, ideally each survivor woulddiffer from the previous survivor only in the lowest-indexed element(corresponding to the most-recent symbol). Where other elements of themost-recent survivor differ from corresponding elements of the previoussurvivor, such difference indicates that there is an error in thoseelements (either in the most-recent survivor or in the previoussurvivor). Given the convolutional nature of the partial responsesignal, symbols at higher indexes in the buffer are more reliable. Thusthe symbol values will tend to converge as they move toward the right inFIG. 8C.

Shown are the contents of example symbol buffer 310 at times n−3, n−2,n−1, and n. At time n−3, a symbol survivor having values α,β,χ,δ isstored in the symbol buffer 310. Accordingly, as shown in FIG. 8D, thevalue of signal 317 at time n−3 is ‘α’ and the value of signal 132 is‘δ.’ At time n−2, a new symbol survivor having values δ,β,β,χ is storedin the symbol buffer 310. Accordingly, as shown in FIG. 8D, the value ofsignal 317 at time n−2 is ‘δ’ and the value of signal 132 is ‘χ.’ Attime n−1, a new symbol survivor having values χ,δ,β,β is stored in thesymbol buffer 310. Accordingly, as shown in FIG. 8D, the value of signal317 at time n−1 is ‘χ’ and the value of signal 132 is ‘β.’ At time n, anew symbol survivor having values β,χ,δ,β is stored in the symbol buffer310. Accordingly, as shown in FIG. 8D, the value of signal 317 at time nis ‘β’ and the value of signal 132 is ‘β.’ Thus, in the example scenariodepicted in FIG. 8C, the value in the first element of the symbol buffer310 at time n−3 was erroneous and the symbol did not converge until itreached the second element (q=2) of the buffer 310. That is, at time n−2the symbol changed from α to β and then remained β at times n−1 and n.This illustrates the consequence of taking signal 317 from the firstelement of the symbol buffer 310 and taking the signal 132 from thefourth element of the symbol buffer 312. Namely, the signal 317 has lessdelay than the signal 132 but is also more error prone than the signal132.

In FIG. 8D, the values of the signals are shown for times n−3 to timen+3. The dashed lines illustrate the delay between the signal 317 andthe signal 132.

FIG. 9A is a flowchart illustrating an example process for carrierrecovery and phase error correction using a partial response feedbacksignal. The process begins with block 902 in which a received partialresponse signal is processed via a non-linear circuit (e.g., front-end108), via an input filter (e.g., filter 109) and a timing pilot removalcircuit (e.g., circuit 110). In block 904, the signal resulting from theprocessing of block 902 is equalized (e.g., via equalizer 202), wherethe equalization is based on a first partial response feedback signal(e.g., signal 201). In block 906, the phase error of the equalizedpartial response signal is corrected (e.g., via phase adjust circuit206) based on a second partial response feedback signal (e.g., signal207). In block 908, samples of the phase corrected partial response(e.g., sampled at the symbol frequency) are buffered (e.g., in buffer212). In block 910, the buffered samples are input to a sequenceestimation process (e.g., performed by sequence estimation circuit 112)in which metrics are calculated based on the buffered samples of thephase corrected partial response signal (e.g., PR1) and based on aplurality of symbol candidates (e.g., SC_(n) ¹ . . . SC_(n) ^(M×Su×P))and one or more phase candidates (e.g., PC_(n) ¹ . . . PC_(n)^(M×Su×P)). In block 912, a best symbol candidate and best phasecandidate are selected based on the calculated metrics. In block 914,the best symbol candidate is written to a symbol buffer (e.g., buffer310) and the best phase candidate is written to a phase buffer (e.g.,buffer 312). In block 916, a vector of one or more symbols stored in thesymbol buffer 310 (e.g., L symbols beginning at index q1) is output forgeneration of the second feedback signal. In block 918, the vectoroutput in block 916 is convolved (e.g., by circuit 316 b) with tapcoefficients (e.g., tap coefficients corresponding to response ĥ) togenerate a partial response signal (e.g., signals 209). In block 920, anon-linearity model (e.g., modeling the nonlinearity of the non-linearcircuit via which the symbols were processed in block 1002) is appliedto the partial response signal generated in block 918, resulting in thesecond partial response feedback signal.

FIG. 9B is a flowchart illustrating an example process for equalizationof a partial response signal using a partial response feedback signal.The process begins with block 952 in which a received partial responsesignal is processed via a non-linear circuit (e.g., front-end 108), viaan input filter (e.g., filter 109) and a timing pilot removal circuit(e.g., circuit 110). In block 954, the signal resulting from theprocessing of block 952 is equalized (e.g., via equalizer 202), wherethe equalization is based on a first partial response feedback signal(e.g., signal 201). In block 956, the phase error of the equalizedpartial response signal is corrected (e.g., via phase adjust circuit206) based on a second partial response feedback signal (e.g., signal207). In block 958, samples of the phase corrected partial response(e.g., sampled at the symbol frequency) are buffered (e.g., in buffer212). In block 960, the buffered samples are input to a sequenceestimation process (e.g., performed by sequence estimation circuit 112)in which metrics are calculated based on the buffered samples of thephase corrected partial response signal (e.g., PR1) and based on aplurality of symbol candidates (e.g., SC_(n) ¹ . . . SC_(n) ^(M×Su×P) )and one or more phase candidates (e.g., PC_(n) ¹ . . . PC_(n)^(M×Su×P)). In block 962, a best symbol candidate and best phasecandidate are selected based on the calculated metrics. In block 964,the best symbol candidate is written to a symbol buffer (e.g., buffer310) and the best phase candidate is written to a phase buffer (e.g.,buffer 312).

In block 966, a vector of one or more symbols of the symbol buffer(e.g., L symbols beginning at index q2) is output for generation of thefirst feedback signal. In block 968, a value of the phase buffer (e.g.,at index q3=q2) is output for generation of the first feedback signal.In block 970, the vector output in block 966 is convolved (e.g., bycircuit 316 a) with tap coefficients (e.g., tap coefficientscorresponding to response ĥ) to generate a partial response signal(e.g., signal 315 a). In block 972, a phase correction is applied (e.g.,by circuit 314) to the partial response signal generated in block 970based on the value output from the phase buffer in block 968. The resultof block 970 is a phase-adjusted partial response signal (e.g., signal205). In block 974, a non-linearity model (e.g., modeling thenonlinearity of the non-linear circuit via which the symbols wereprocessed in block 1002) is applied to the partial response signalgenerated in block 918, resulting in a non-linearized partial responsesignal. In block 976, the non-linearized partial response signalgenerated in block 974 is subtracted from the equalizer output togenerate the first partial response feedback signal.

FIG. 10 is a flowchart illustrating adaptation of feedback loopbandwidth. The process begins with block 1002 when a partial responsesignal received by a receiver (e.g., a receiver comprising components108, 109, 110, 112, and 114). Next, in block 1004, characteristics(e.g., signal-to-noise ratio, symbol error rate, bit error rate, etc.)of the received signal are measured (e.g., in the front-end 108 and/orby a digital signal processing circuit downstream from the de-mapper114). For example, the metrics calculated by the sequence estimationcircuit 112 may be used in generating an estimate of SNR and/or phaseerror. In block 1006, a value one or more parameters (e.g., Q, q1, q2,and/or q3) may be configured based on the characteristics measured inblock 1004. In this manner, parameters may be configured during run-time(e.g., in, or near, real-time) based, for example, on recently receivedsignals and/or signals currently being received. Parameters maybeconfigured as needed based on the bandwidth of the feedback loops thatcontrol an equalizer (e.g., 202) and/or a carrier recovery circuit.(e.g., 208). In block 1008, sequence estimation may be performed on thereceived signal using the parameter values set in block 1006.

In an example implementation, a receiver may receive an inter-symbolcorrelated (ISC) signal (e.g., signal 122). The receiver may equalize,via an equalizer (e.g. 202), the received ISC signal to generate anequalized signal (e.g., 222). The equalization may be based on a firstinter-symbol correlated (ISC) feedback signal (e.g., 203). The receivermay correct, via a phase adjuster (e.g., 206) based on a second ISCfeedback signal (e.g., 207), a phase error of the equalized signal togenerate a phase-corrected equalized signal (e.g., 226). One or both ofthe first ISC feedback signal and the second ISC feedback signals may bepartial response signals generated via a convolution with tapcoefficients. Generation of the first ISC feedback signal may compriseconvolution of an estimated symbol vector (e.g., L symbols, beginning atindex q2, from the symbol buffer 310) with a plurality of tapcoefficients, the convolving resulting in a first estimated ISC signal(e.g., 315 a). Generation of the first ISC feedback signal may comprisephase adjustment of the first estimated ISC signal to generate a secondestimated ISC signal. Generation of the first ISC feedback signal maycomprise application (e.g., in circuit 316 a) of a model of a non-linearcircuit (e.g., 106 and/or 108) through which the received signal passedto the second estimated ISC signal. The tap coefficients may be based ontap coefficients of a partial response filter (e.g., 104 and/or 109).Generation of the second ISC feedback signal may comprise convolution ofan estimated symbol vector (e.g., L symbols, beginning at index q1, fromthe symbol buffer 310) with a plurality of tap coefficients, theconvolution resulting in a third estimated ISC signal (e.g., 317).Generation of the second ISC feedback signal may comprise application(e.g., in circuit 316 a) of a model of a non-linear circuit (e.g., 106and/or 108) through which the received signal passed to the thirdestimated ISC signal. Circuitry of the receiver may control, duringrun-time of the equalizer, a bandwidth of one or both of a firstfeedback loop comprising the first ISC feedback signal, and a secondfeedback loop comprising the second ISC feedback signal, the controllingbeing based on a measured performance indicator (e.g., an indicator ofchannel conditions and/or receiver performance such as noise levels,signal to noise ration (SNR), symbol error rate (SER), value of thesignal 228, etc.). The control may comprises adjustment one or morebuffer index values (e.g., q1, q2, and/or q3) wherein a first one of thebuffer index values (e.g., q2) corresponds to a buffer element that isread for generating the first ISC feedback signal, and a second one ofthe buffer index values (e.g., q1) corresponds to a buffer element thatis read for generating the second ISC feedback signal.

Other implementations may provide a non-transitory computer readablemedium and/or storage medium, and/or a non-transitory machine readablemedium and/or storage medium, having stored thereon, a machine codeand/or a computer program having at least one code section executable bya machine and/or a computer, thereby causing the machine and/or computerto perform the processes as described herein.

Methods and systems disclosed herein may be realized in hardware,software, or a combination of hardware and software. Methods and systemsdisclosed herein may be realized in a centralized fashion in at leastone computing system, or in a distributed fashion where differentelements are spread across several interconnected computing systems. Anykind of computing system or other apparatus adapted for carrying out themethods described herein is suited. A typical combination of hardwareand software may be a general-purpose computing system with a program orother code that, when being loaded and executed, controls the computingsystem such that it carries out methods described herein. Anothertypical implementation may comprise an application specific integratedcircuit (ASIC) or chip with a program or other code that, when beingloaded and executed, controls the ASIC such that is carries out methodsdescribed herein.

While methods and systems have been described herein with reference tocertain implementations, it will be understood by those skilled in theart that various changes may be made and equivalents may be substitutedwithout departing from the scope of the present method and/or system. Inaddition, many modifications may be made to adapt a particular situationor material to the teachings of the present disclosure without departingfrom its scope. Therefore, it is intended that the present method and/orsystem not be limited to the particular implementations disclosed, butthat the present method and/or system will include all implementationsfalling within the scope of the appended claims.

1-20. (canceled)
 21. A method comprising: in an electronic receiver:receiving a signal; converting said received to a symbol-domain signal;generating an estimate of symbols transmitted to generate said receivedsignal; and generating an error signal indicative of an error in saidgenerated estimate of said symbols, wherein said generating said errorsignal comprises nonlinearly distorting said estimate of said symbols.22. The method of claim 21, comprising, as part of said converting saidreceived signal to said symbol-domain signal, equalizing said receivedsignal to generate an equalized signal.
 23. The method of claim 21,comprising, as part of said generating said error signal, calculating aEuclidean distance between a feedback signal and said equalized signal.24. The method of claim 21, comprising: generating a feedback signalfrom said symbol-domain signal; and phase adjusting said equalizedsignal based on said feedback signal.
 25. The method of claim 24,comprising, as part of said generating said feedback signal, convolvingsaid estimate of said symbols with a plurality of tap coefficients. 26.The method of claim 25, comprising determining said tap coefficientsbased on tap coefficients of a filter of a transmitter from which saidreceived signal was received.
 27. The method of claim 21, comprising, aspart of said generating said error signal, processing said estimate ofsaid symbols via a nonlinearity modeling circuit.
 28. The method ofclaim 278, wherein said nonlinearity modeling circuit models anonlinearity of a transmitter from which said received signal wasreceived.
 29. The method of claim 28, wherein said nonlinearity modelingcircuit models a nonlinearity of a front-end of said electronicreceiver.
 30. A system comprising: circuitry for use in an electronicreceiver, the circuitry comprising a nonlinearity modeling circuit andbeing operable to: receive a signal; convert said received signal to asymbol-domain signal; generate an estimate of symbols transmitted togenerate said received signal; and generate an error signal indicativeof an error in said generated estimate of said symbols, wherein saidgeneration of said error signal comprises nonlinearly distorting of saidestimate of said symbols via said nonlinearity modeling circuit.
 31. Thesystem of claim 30, wherein: said circuitry comprises an equalizer; andsaid conversion of said received signal to said symbol-domain signalcomprises equalization, via said equalizer, of said received signal togenerate an equalized signal.
 32. The system of claim 31, wherein saidgeneration of said error signal comprises calculation of a Euclideandistance between a feedback signal and said equalized signal.
 33. Thesystem of claim 31, wherein said circuitry is operable to: generate afeedback signal from said symbol-domain signal; and phase adjust saidequalized signal based on said feedback signal.
 34. The system of claim31, wherein said generation of said feedback signal comprisesconvolution of said estimate of said symbols signal with a plurality oftap coefficients.
 35. The system of claim 31, wherein said circuitry isoperable to determine said tap coefficients based on tap coefficients ofa filter of a transmitter from which said received signal was received.36. The system of claim 31, wherein said generation of said feedbacksignal comprises processing of said estimate of said symbols via saidnonlinearity modeling circuit.
 37. The system of claim 38, wherein saidnonlinearity modeling circuit models a nonlinearity of a transmitterfrom which said received partial-response-domain signal was received.38. The system of claim 38, wherein said nonlinearity modeling circuitmodels a nonlinearity of a front-end of said electronic receiver.